Advances and challenges in VLSI designs for nanotechnology

Amit Kumar

Bhaskaracharya College of Applied Sciences, University of Delhi

Since the advent of nanotechnologies, Moore's law has been challenged through advances in molecular science and fabrication techniques, as the feature size reached the molecular scales where classical physics is impossible to explain and quantum mechanics takes over. The present trend is toward VLSI design with CMOS as it is the most efficient at lower prices and offers higher density. The scaling theory is used when VLSI designs move from old fabrication technology to new fabrication technology resulting from shrinking circuit sizes. CMOS technology now no longer follows scaling theories since we have reached the sub-nanometer regime. A short channel effect occurs when channel lengths of aggressively scaled MOSFETs are comparable to the sum of the source and drain depletion layer thicknesses. The problem of short-channel effects can now be solved by proposing alternative structures and materials. In this paper, we discuss a few of these alternatives along with the current situation (covering the past decade) and possible future trends. This paper summarizes the VLSI design developments in last decade and near future opportunities due to advent in nanotechnology.